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Digital circuit design (logic circuit design) and verification - LSI design (semiconductor design)

Fully utilizing the latest design and verification technologies.

I have been involved in many semiconductor designs and have honed my skills in logic circuit design and verification technology. Based on that experience and achievements, I provide services across various processes in FPGA design/logic design development, including architecture design (detailed design), logic design, logic verification, and physical verification. I also accept development methods such as FPGA development and Model-Based Development (MBD) upon request. Additionally, I flexibly adapt to design flows such as waterfall and agile according to the project's objectives and characteristics. To quickly respond to the rapid large-scale integration of circuits, I skillfully use not only traditional HDL but also high-level modern languages such as C/C++ and SystemC, promoting further efficiency. - FPGA Design - ASIC Development - Design Achievements I provide refined services in architecture design, logic design, and logic verification with polished digital design and verification technology. - Development of sensor image evaluation systems for automotive applications - Development of a platform for hardware implementation of OpenCV for automotive applications - Development of camera systems for industrial applications - CIS logic circuit design - Mixed-Signal LSI logic circuit design - Digital signal processing design

  • ASIC
  • Other semiconductors

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[Information] Shirutoku Report No. 86 # Asynchronous Input Requires Measures

Caution is needed! It is important to properly address metastability measures during the design phase!

★★Shirutoku Report: Useful Information You Should Know★★ Digital circuits consist of synchronous circuits that are synchronized with a clock and asynchronous circuits that are not. In synchronous circuits, flip-flops (FF) used have timing specifications such as setup time (tSU) and hold time (tH) established as requirements for stable operation between the clock and input signals. This time, we will explain the handling of asynchronous input signals, which require caution in digital circuit design such as FPGA. 【Contents】 ■ Factors that cause logical circuits to malfunction ■ Measures to prevent impact on circuit operation ■ The number of flip-flops needs to be optimized ■ It is important to properly implement metastability measures during the design phase *For more details, please refer to the PDF materials or feel free to contact us.*

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